1. Field of the Invention
The present invention relates to a pipelined analog-to-digital converter having a plurality of 1.5-bit converter stages cascaded to each other.
2. Description of the Background Art
At first, reference will be made to FIG. 2A, which is a schematic block diagram showing a conventional pipelined analog-to-digital converter disclosed by U.S. Pat. No. 6,437,608 B1 to Miyabe et al., and U.S. Pat. No. 5,274,377 to Matsuura et al. FIG. 2B is a graph plotting the input/output characteristics of each 1.5-bit converter stage (STG) shown in FIG. 2A. In the following, signals are indicated with reference numerals of connections on which they are conveyed.
The pipelined analog-to-digital converter 10 shown in FIG. 2A showing its overall constitution includes a sample and hold amplifier (SHA) 12, a plurality of 1.5-bit cascaded converter stages 14, 16 and 18 which are interconnected in cascade on the output side of the sample and hold amplifier 12, an analog-to-digital converter (ADC) unit 20 which is connected to the output port 44 of the last one 18 of the cascaded converter stages, and an error correction logic (ECL) 22.
The sample and hold amplifier 12 is adapted for sampling an analog input signal 24 at a predetermined time interval in response to a clock signal CK, and holds resulting samples. The sample and hold amplifier 12 transfers the resulting samples 28 to the initial converter stage 14 in the form of input voltage VI.
The initial converter stage 14 is adapted for comparing the input voltage 28 having its value VI to reference voltages 30 and 32 having the values +REF/4 and −REF/4, respectively, FIG. 3, to determine in which of three voltage ranges the input voltage VI falls, namely, a voltage range A not higher than −REF/4, a voltage range B between −REF/4 and +REF/4 or a voltage range C not lower than +REF/4, FIG. 2B. The converter stage 14 in turn outputs the result of determination as a 1.5-bit digital signal 34 to the error correction logic ECL. Thus, the converter stage 14 outputs an output voltage 36 which is twice as high as the difference between the input voltage 28 and a voltage corresponding to either of the digital signals, i.e. −REF, 0 or +REF, as an output signal 36 on its downstream side. The other converter stages 16-18 work in a similar way to supply the error correction logic 22 with digital signals 38 and 40, respectively, and the respective downstream sides with output voltages 42 and 44. The digital signals from the converter stages 14, 16-18 are actually composed of two bits, but they are expressed as 1.5-bit signals in this description in consideration that there are only three information quantities output from each of the converter stages. Similarly, the signals of three kinds of information will be hereinafter referred to as “1.5-bit signals.”
The ADC unit 20 is adapted for converting the voltage 44 from the converter stage 18 to a two-bit digital signal 46. The error correction logic 22 is adapted for receiving the digital signal 46 from the ADC unit 20 as well as signals 34, 38 and 40 from the converter stages 14, 16 and 18, respectively, and processing them to output an ultimate digital signal 50.
FIG. 3 shows an example of conventional converter stage (STG). The converter stage 14, 16 or 18 includes an analog-to-digital converter (ADC) section 52, an encoder (ENC) 54, a digital-to-analog converter (DAC) section 56, and an amplifier (AMP) 58.
The ADC section 52 is adapted for receiving an input voltage VI from its upstream side and generating 1.5-bit signals based on the input voltage VI. Specifically, the ADC section 52 includes comparators 59 and 60 (CMPs), which compare the input voltage VI to the reference voltages +REF/4. The comparator 59 is adapted for outputting a signal S1 at its high level “H”, such as a power supply voltage VDD, when VI>+REF/4, or at its low level “L”, such as ground potential GND, when VI≦+REF/4. The comparator 60 is adapted for outputting a signal S2 at its level “H”, when VI>−REF/4, or at its level “L”, when VI≦−REF/4. Thus, the combinations of output signals S1 and S2 output from the ADC section 52 are (H, H), (L, H) and (L, L) when VI>+REF/4, +REF/4≧VI>−REF/4 and VI≦−REF/4, respectively. The ADC section 52 supplies these 1.5-bit signals to the error correction logic 50 and the encoder 54.
The encoder 54 is adapted for generating signals X, Y and Z in response to the signals S1 and S2, and the clock signal CK to transfer the signals X, Y and Z to the DAC section 56. The encoder 54 includes dual-input NAND gates 76 and 78, inverters 80 and 82, and a tri-input NAND gate 84. The NAND gate 76 receives the signal S1, while the NAND gate 84 receives an inverted signal into which the inverter 82 inverted the the signal S1. The NAND gate 84 receives the signal S2, while the NAND gate 78 receives a signal into which the inverter 80 inverted the signal S2. The NAND gates 76, 78 and 84 also receive the clock signal CK commonly. The NAND gates 76, 78 and 84 output the signals X, Y and Z, respectively.
With the above logics constitution, the combination of signals X, Y and Z produced from the encoder 54 depends on the signals S1 and S2 from the ADC section 52 and the clock signal CK, as will read below:
for CK=“L”, signals X, Y and Z are all “H” independently of signals S1 and S2, and
for CK=“H”,
(X, Y, Z)=(L, H, H) for (S1, S2)=(H, H),
(X, Y, Z)=(H, H, L) for (S1, S2)=(L, H) and
(X, Y, Z)=(H, L, H) for (S1, S2)=(L, L).
The DAC section 56 is adapted for outputting a reference voltage +REF, −REF or 0 as a voltage 86 in response to the signals X, Y and Z from the encoder 54. Specifically, the DAC section 56 includes switches 88, 90 and 92, which are controlled by the signals X, Y and Z, respectively. When the signal X turns on the switch 88, the voltage 86 will be equal to −REF. When the signal Y turns on the switch 90, it will be equal to +REF, and when the signal Z turns on the switch 92, it will be equal to zero. Each of the switches 88 to 92 is set so as to be turned on or off in response to its corresponding control signal X, Y or Z is “L” or “H”, respectively. When the signals X, Y and Z are all “H”, the voltage 86 ceases to output.
The amplifier 58 is adapted for amplifying the voltage difference between the input voltage VI and the output voltage 86 from the DAC section 56 by a factor of two, and outputting a resulting amplified voltage VO. The amplifier 58 includes switches 94, 96 and 98, capacitors 100 and 102 of the same capacity, and an operational amplifier (OP) 104. The switches 94 and 96 are adapted for selecting the input voltage VI when the clock signal CK is “L”, while respectively selecting the output voltage VO and the output voltage 86 of the DAC section 56 when the clock signal CK is “H”. Specifically, the switches 94 and 96 have output ports connected to a node 106 via the capacitors 100 and 102, respectively. The switch 98 is, when the clock signal CK is “L”, turned on to connect the node 106 to the ground voltage (GND). The operational amplifier 104 is adapted for amplifying the voltage on the node 106 to deliver the resulting amplified voltage VO to one of the converter stages (STGs) interconnected on its downstream side.
The operation of the pipelined analog-to-digital converter will now be described, which includes the multiple converter stages connected in cascade.
The analog input signal 24 is sampled and held by the sample and hold amplifier 12, in response to the clock signal CK, and thereafter delivered as the input voltage 28 to the initial converter stage 14. In the initial converter stage 14, the input voltage 28 is compared by the ADC section 52 to the reference voltages +REF/4 and −REF/4. The result of comparison is delivered as the signals S1 and S2 to the error correction logic 22 and to the encoder 54 of the converter stage 14.
In the encoder 54, the signals X, Y and Z are generated in dependent upon a combination of clock signal CK and signals S1 and S2. The signals X, Y and Z are delivered to the DAC section 56, from which the reference voltage +REF, −REF or 0 is generated as the voltage 86, in dependent on a combination of signals X, Y and Z. The so generated reference voltage is supplied to the amplifier 58.
In the amplifier 58, a voltage corresponding to the input voltage 28 minus the output voltage 86 is amplified to be doubled by switching the capacitor 100 or 102 in response to the clock signal CK to output the output voltage 36 indicating this doubled voltage.
Thus, as shown in FIG. 2B, if the input voltage 28 of the converter stage 14 is not higher than the value −REF/4, the output voltage 36 ranges between the values −REF and +REF/2. If the input voltage 28 ranges between values −REF/4 and +REF/4, the output voltage 36 ranges between values −REF/2 and +REF/2. If the input voltage 2B is not less than value +REF/4, the output voltage 36 ranges between values −REF/2 and +REF. The output voltage 36 is delivered to the next converter stage 16 as the input voltage 36 of the latter.
In this manner, a 1.5-bit digital signal is output from each converter stage in response to the clock signal CK. The so generated digital signals are input to the error correction logic 22 to be pipelined to generate a predetermined number of bits of the digital signal 50.
In each converter stage (STG) described above referring to FIG. 3, the encoder 54 generates the signals X, Y and Z for the DAC section 56, on the premise that there are only three combinations of signals S1 and S2 supplied from the ADC section 52, namely (H, H), (L, H) and (L, L). Thus, if there is logical incongruence in a combination of signals S1 and S2, that is, S1=“H” and S2=“L”, there will be an abnormal combination of signals X, Y and Z generated, thereby causing the DAC section 56 to erroneously operate.
More specifically, in the encoder 54 of FIG. 3, if the signals S1 and S2 delivered are respectively “H” and “L”, and the clock signal CK is “H”, the output signals X, Y and Z will be respectively “L”, “L” and “H”. Because both the signals X and Y are “L”, the switches 88 to 92 in the DAC section 56 will be all turned on. This short-circuits the current path between the reference voltages +REF and −REF via the switches 88 to 92, with the result that the output voltage 86 is of an abnormal value. Even if a combination of signals S1 and S2 reverts to its normal combination of values by the next input voltage VI, it will take much time until the voltage 86 reverts to its normal combination. During this time interval, normal operations for conversion may not be attained.
It should be noted that the situation in which logically incongruent signals S1 and S2 are output from the ADC section 52 is hardly liable to occur in general in the case of ADC sections manufactured by a normal production process. However, the situation may arise in such a case that ADC sections having comparators 59 and 60 or circuits for generating voltages +REF/4 and −REF/4 suffer from variations in characteristics due to changes in the production process or the like. Heretofore, such ADC sections are discarded as rejects in the course of product inspection, thus lowering the yield.